Dual Common Interface Hardware Controller The T90-FJR, also known as the CIMaXTM controller, is the hardware extension of SCM Microsystems' second generation Common Interface integration package (CI Pack+TM). It enables CI Driver software to directly address two complete independent Common Interface modules. As such, it contributes to offer an optimized, homogeneous and complete solution for digital TV receiver manufacturer that wants to quickly implement the Common Interface. This document contains several application notes that give accurate information on the hardware designer for implementing the CIMaXTM circuit into its digital TV receiver. It describes how to connect the CIMaXTM to its surrounding environment (modules, processor...). For each connection type (e.g. modules, host...), several schematics are provided corresponding to the alternate solutions provided by the CIMaXTM. Pins marked with a cross (X) should be left unconnected. Those marked with a square ( . ) may be connected but connection is part of another schematic and is not shown on the current schematic. Application Notes T90FJR (CIMaXTM) Rev. A - 25-Oct-01 1 T90FJR System Diagram CIMaXTM I2 C Interface I2 C TS Module A Module A TS in TS interface TS out HOST RST,CLK Interrupts Management INT TS Module B RD,WR,CS WAIT/ACK Module B UCSG A[25..15] Ext Ext CS IT Host processor address and data busses Address/ Data Buffers 2 Rev. A - 25-Oct-01 Module Interface Connection of module sockets to CIMaXTM is achieved simply by connecting directly all the MPEG transport stream signals and common interface control signals of each module directly to the corresponding pins of the CIMaXTM. The address and data busses are connected to the host processor busses through standard buffers. The following Bill Of Materials (BOM) applies: Quantity Description 1x CIMaXTM (103563) 2x PCMCIA Connector 2x 74HCT373 1x 74HCT245 Figure 1. CiMaXTM connection to DVB modules JP1 20 19 46 47 48 49 50 53 54 55 56 U3 36 38 51 64 109 65 50 49 48 47 46 45 44 43 42 41 40 63 62 61 60 59 58 57 56 55 54 53 34 35 31 30 33 32 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 69 68 67 66 37 9 39 52 8 86 VCC_ARRAY VCC_PROC VCC_TSI VCC_TSO VCC_DVB1 VCC_DVB2 MICLK MISTRT MIVAL MDI7 MDI6 MDI5 MDI4 MDI3 MDI2 MDI1 MDI0 MOCLK MOSTRT MOVAL MDO7 MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 MDO0 MPEG Output stream to module MPEG input stream from front end MPEG output stream to decoder RST CLK SCL SDA I2C bus SA1 SA0 I2C address A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 CS RD/DIR WR/STR WAIT/AC K INT EXTCS EXTINT Host proc. address bus Host proc. Control signals Ext periph A MPEG input stream from module A Module A control signals control signals to both modules GND_PROC GND_TSI GND_TSO GND_DVB1 GND_DVB2 RSTA CD1A# CD2A# CE1A# CE2A# RDY/IRQA# WAITA# REG# OE# WE# IORD# IOWR# MPEG output stream to module B MPEG input stream from module B MOCLKB MOSTRTB MOVALB MDOB7 MDOB6 MDOB5 MDOB4 MDOB3 MDOB2 MDOB1 MDOB0 buffers control Module B control GND_ARRAY MOCLKA MOSTRTA MOVALA MDOA7 MDOA6 MDOA5 MDOA4 MDOA3 MDOA2 MDOA1 MDOA0 MICLKB MISTRTB MIVALB MDIB7 MDIB6 MDIB5 MDIB4 MDIB3 MDIB2 MDIB1 MDIB0 control DATOE# DATDIR ADOE# ADLE MICLKA MISTRTA MIVALA MDIA7 MDIA6 MDIA5 MDIA4 MDIA3 MDIA2 MDIA1 MDIA0 signals modules power control 110 92 105 116 114 112 107 103 99 96 94 R5 56. 57 62 63 64 65 66 37 38 39 40 41 118 127 125 84 80 78 76 74 5 3 1 61 7 42 9 15 44 45 60 16 120 72 7 82 87 101 122 68 35 34 1 123 88 97 89 90 REG CE1 CE2 OE WE/PGM IORD IOWR INPACK IREQ GND GND GND GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CD1 CD2 VS1 WAIT IOIS16 VPP1 VPP2 RESET VCC VCC 30 31 32 2 3 4 5 6 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 29 28 27 26 25 24 23 22 12 11 8 10 21 13 14 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 36 67 U4 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 G DIR 43 59 33 18 52 18 17 16 15 14 13 12 11 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 19 1 74AHCT24 5 58 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 51 17 2 5 6 9 12 15 16 19 U5 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 OC G R1 3 4 7 8 13 14 17 18 HA0 HA1 HA2 HA3 HA4 HA5 HA6 HA7 1 11 74AHCT37 10k JP2 20 19 46 47 48 49 50 53 54 55 56 R6 56. 117 126 124 83 79 77 75 73 4 2 128 57 62 63 64 65 66 37 38 39 40 41 119 RSTB 71 CD1B# 6 CD2B# 81 CE1B# 85 CE2B# 100 RDY/IRQB# 121 WAITB# VCCEN MOCLK MOVAL MOSTRT MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 D0 D1 D2 D3 D4 D5 D6 D7 PCMCIA SOCKET GND 108 91 104 115 113 111 106 102 98 95 93 MICLK MIVAL MISTRT MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 70 61 7 42 9 15 44 45 60 16 CIMaX 68 35 34 1 GND MICLK MIVAL MISTRT MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 MOCLK MOVAL MOSTRT MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 REG CE1 CE2 OE WE/PGM IORD IOWR INPACK IREQ GND GND GND GND R2 10k D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CD1 CD2 VS1 WAIT IOIS16 VPP1 VPP2 RESET VCC VCC 30 31 32 2 3 4 5 6 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 29 28 27 26 25 24 23 22 12 11 8 10 21 13 14 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 36 67 43 59 33 18 52 MA8 MA9 MA10 MA11 MA12 MA13 MA14 2 5 6 9 12 15 16 19 U6 3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 OC G 3 4 7 8 13 14 17 18 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 1 11 74AHCT37 3 HD[7:0] HA[15:0] Host address and data processor busses 58 51 17 PCMCIA SOCKET R3 10k R4 10k 3 T90FJR Rev. A - 25-Oct-01 T90FJR Power Management The CIMaXTM provides the possibility to control the modules power supply with its VCC output. This output can be configured to drive different types of switches by selecting its structure (open-drain or push-pull) and its active level. In the example below, an LTC1477 from Linear Technology is used to switch the modules power supply. In this case, the output should be programmed to be an active-high push-pull so VCLVL and VCDRV bits in the power control register should be set during power-up initialization procedure before setting LOCK bit. Then, the VCC bit in the power control register controls the VCC switch. For more details on the LTC1477, please refer to the 1995 Linear Databook volume IV from Linear Technology. Other components can be used to switch the power (integrated circuits or transistors) such as MAX869L or MAX890L from MAXIM. The VCLVL and VCDRV bits should be set in accordance with the actual hardware configuration. It is also possible to directly connect the modules VCC permanently to the host's VCC without using the VCC switch facility. In that case, the VCC bit should be set to indicate to the CIMaXTM that the modules are powered so that the buffers can be enabled (when VCC is switched off, the buffers are automatically disabled). 4 Rev. A - 25-Oct-01 The following Bill Of Materials (BOM) applies: Quantity Description 1x CIMaXTM (103563) 2x PCMCIA Connector 2x 74HCT373 1x 74HCT245 1x LTC1477 (or MAX869L or MAX890L) Figure 2. Modules Power Connection JP1 C1 0.1f GND C2 0.1f 20 19 46 47 48 49 50 53 54 55 56 GND VCC_TSI 3.3V VCC_PROC U1 VCC_TSO 36 38 51 64 109 65 C3 0.1f GND GND C4 0.1f GND C5 0.1f 50 49 48 47 46 45 44 43 42 41 40 C6 0.1f GND 63 62 61 60 59 58 57 56 55 54 53 34 35 31 30 33 32 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 69 68 67 66 37 9 39 52 8 86 VCC_ARRAY VCC_PROC VCC_TSI VCC_TSO VCC_DVB1 VCC_DVB2 MICLK MISTRT MIVAL MDI7 MDI6 MDI5 MDI4 MDI3 MDI2 MDI1 MDI0 MOCLK MOSTRT MOVAL MDO7 MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 MDO0 MPEG input stream from front end MPEG output stream to decoder RST CLK SCL SDA I2C bus SA1 SA0 I2C address A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 Host proc. address bus CS RD/DIR WR/STR WAIT/ACK INT Host proc. control signals EXTCS EXTINT Ext periph control DATOE# DATDIR ADOE# ADLE buffers control GND_ARRAY GND_PROC GND_TSI GND_TSO GND_DVB1 GND_DVB2 MPEG output stream to module A MICLKA MISTRTA MIVALA MDIA7 MDIA6 MDIA5 MDIA4 MDIA3 MDIA2 MDIA1 MDIA0 MPEG input stream from module A MOCLKA MOSTRTA MOVALA MDOA7 MDOA6 MDOA5 MDOA4 MDOA3 MDOA2 MDOA1 MDOA0 module A control signals control signals to both modules MPEG output stream to module B MPEG input stream from module B module B control signals modules power control RSTA CD1A# CD2A# CE1A# CE2A# RDY/IRQA# WAITA# REG# OE# WE# IORD# IOWR# MICLKB MISTRTB MIVALB MDIB7 MDIB6 MDIB5 MDIB4 MDIB3 MDIB2 MDIB1 MDIB0 110 92 105 116 114 112 107 103 99 96 94 57 62 63 64 65 66 37 38 39 40 41 118 127 125 84 80 78 76 74 5 3 1 61 7 42 9 15 44 45 60 16 120 72 7 82 87 101 122 68 35 34 1 VCC 123 88 97 89 90 108 91 104 115 113 111 106 102 98 95 93 VCCEN REG CE1 CE2 OE WE/PGM IORD IOWR INPACK IREQ GND GND GND GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CD1 CD2 VS1 WAIT IOIS16 VPP1 VPP2 RESET VCC VCC 30 31 32 2 3 4 5 6 29 28 27 26 25 24 23 22 12 11 8 10 21 13 14 U2 20 C7 0.1f GND GND 3 2 7 6 4 Vins Vin1 Vin2 Vin3 EN LTC1477 1 Vout 8 Vout GND 2 3 4 5 6 7 8 9 36 67 VCC A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 G DIR 18 17 16 15 14 13 12 11 19 1 74AHC245 43 59 33 18 52 U3 20 58 C8 0.1f 51 17 GND U5 C9 0.1f 2 5 6 9 12 15 16 19 + C10 1f VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 OC G 3 4 7 8 13 14 17 18 1 11 74AHCT373 5 GND GND JP2 20 19 46 47 48 49 50 53 54 55 56 57 62 63 64 65 66 37 38 39 40 41 119 71 6 81 85 100 121 70 61 7 42 9 15 44 45 60 16 CIMaX GND 68 35 34 1 GND 5 MOCLK MOVAL MOSTRT MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 D0 D1 D2 D3 D4 D5 D6 D7 PCMCIA SOCKET MODULE A GND 117 MOCLKB 126 MOSTRTB 124 MOVALB 83 MDOB7 79 MDOB6 77 MDOB5 75 MDOB4 73 MDOB3 4 MDOB2 2 MDOB1 128 MDOB0 RSTB CD1B# CD2B# CE1B# CE2B# RDY/IRQB# WAITB# MICLK MIVAL MISTRT MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 MICLK MIVAL MISTRT MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 MOCLK MOVAL MOSTRT MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 REG CE1 CE2 OE WE/PGM IORD IOWR INPACK IREQ GND GND GND GND D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CD1 CD2 VS1 WAIT IOIS16 VPP1 VPP2 RESET VCC VCC 30 31 32 2 3 4 5 6 29 28 27 26 25 24 23 22 12 11 8 10 21 13 14 U4 20 C11 0.1f GND 2 5 6 9 12 15 16 19 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 OC G 3 4 7 8 13 14 17 18 1 11 74AHCT373 36 67 43 59 33 18 52 58 51 17 PCMCIA SOCKET MODULE B T90FJR Rev. A - 25-Oct-01 T90FJR Host side connection Reset, clock At power-up the whole chip is reset by activating the RESET pin (of the chip). The clock must be stable before reset deactivation. The clock input should be connected to a 27MHz clock source. Configuration interface (I2C) Access to the CIMaXTM internal registers is provided through an I2C serial interface as defined in [5]. The I2C component address is configurable using SA1 and SA0 pins as described in page 8, between 80, 82, 84 and 86 hex. Though, SA1 and SA0 pins should be connected to VCC or GND depending on the desired address for the CIMaXTM. Thanks to this configurable address, it is possible to connect several (up to 4) CIMaXTM on the same board. SCL and SDA pins should be connected to the host I2C bus. Host processor addresses The host's high order addresses A[25:15] should be connected to the CIMaXTM in order to automatically choose between the modules or to access to memory cards. Host processor bus control signals The host processor bus control signals depend on the processor used. Different configurations are given below. MPEG signals The MPEG inputs of the CIMaXTM should be connected to the MPEG source of the host (e.g. satellite or cable front-end) or from another CIMaXTM (see "Chaining. CIMaXTM" ). The MPEG signals coming from this source should respect the timing limits defined in the DVB standard. The MPEG outputs can be connected to any MPEG compliant destination (e.g. MPEG decoder) or another CIMaXTM. The MPEG output signals are guaranteed to meet the provided timing specifications that the modules inserted in the daisy chain also respect those timings. 6 Rev. A - 25-Oct-01 Schematic Diagram Figure 3. Connecting CiMaXTM to the host U1 36 38 51 64 109 65 MPEG Clock input MPEG packet start input MPEG valid data input MPEG input transport stream MPEG data input MPEG clock output MPEG packet start output MPEG valid data output MPEG output transport stream Global signals MPEG data output Host global reset Host 27MHz clock 63 62 61 60 59 58 57 56 55 54 53 34 35 31 30 SCL SDA I2C bus 50 49 48 47 46 45 44 43 42 41 40 I2C address (connect either to VCC or GND) 33 32 29 28 27 26 25 24 23 22 21 20 19 Host processor address bus HA[25:15] 18 17 16 15 14 13 12 69 68 67 66 37 9 39 52 8 86 Title Connecting CIMaX to the host Size A4 7 Document Number {Doc} Rev 1.1 VCC_ARRAY VCC_PROC VCC_TSI VCC_TSO VCC_DVB1 VCC_DVB2 MICLK MISTRT MIVAL MDI7 MDI6 MDI5 MDI4 MDI3 MDI2 MDI1 MDI0 MOCLK MOSTRT MOVAL MDO7 MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 MDO0 MPEG input stream from front end MPEG output stream to decoder RST CLK SCL SDA I2C bus SA1 SA0 I2C address A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 Host proc. address bus CS Host proc. RD/DIR control WR/STR WAIT/ACK signals INT EXTCS EXTINT Ext periph control DATOE# DATDIR ADOE# ADLE GND_ARRAY GND_PROC GND_TSI GND_TSO GND_DVB1 GND_DVB2 MPEG output stream to module A MICLKA MISTRTA MIVALA MDIA7 MDIA6 MDIA5 MDIA4 MDIA3 MDIA2 MDIA1 MDIA0 MPEG input stream from module A MOCLKA MOSTRTA MOVALA MDOA7 MDOA6 MDOA5 MDOA4 MDOA3 MDOA2 MDOA1 MDOA0 module A control signals control signals to both modules RSTA CD1A# CD2A# CE1A# CE2A# RDY/IRQA# WAITA# REG# OE# WE# IORD# IOWR# MPEG output stream to module B MICLKB MISTRTB MIVALB MDIB7 MDIB6 MDIB5 MDIB4 MDIB3 MDIB2 MDIB1 MDIB0 MPEG input stream from module B MOCLKB MOSTRTB MOVALB MDOB7 MDOB6 MDOB5 MDOB4 MDOB3 MDOB2 MDOB1 MDOB0 buffers control module B control signals modules power control RSTB CD1B# CD2B# CE1B# CE2B# RDY/IRQB# WAITB# VCCEN 110 92 105 116 114 112 107 103 99 96 94 118 127 125 84 80 78 76 74 5 3 1 120 72 7 82 87 101 122 123 88 97 89 90 108 91 104 115 113 111 106 102 98 95 93 117 126 124 83 79 77 75 73 4 2 128 119 71 6 81 85 100 121 70 CIMaX T90FJR Rev. A - 25-Oct-01 T90FJR Chaining CIMaXTM The CIMaXTM offers control for two CI compliant modules. However, it is possible to use multiple CIMaXTM to add more DVB-CI slots. The CIMaXTM must be individually identified by their I2C address in order for the host processor to be able to access the desired CIMaXTM. There are two I2C address pins available on the chip thus providing the ability to connect up to four CIMaXTM. The MPEG transport stream coming from front-end is input to the first CIMaXTM and the MPEG transport stream of this CIMaXTM is then input to the next CIMaXTM. The MPEG output stream of the last CIMaXTM of the chain is finally input to the MPEG decoder. The host processor control signals coming from the processor are input to all the CIMaXTM in the chain, including the high order addresses. The CIMaXTM address decoding registers should be set differently in each CIMaXTM to differentiate between all the available modules. The outputs of the CIMaXTM (INT, WAIT) should be connected together on a wired-or basis and should be configured to be open-drain (source) driven. The schematic on the next page gives an example of connecting two CIMaXTM in the same environment. The I2C address of the first one is fixed to 80hex and the second is 84hex. 8 Rev. A - 25-Oct-01 Figure 4. Chaining CIMaXTM U1 36 38 51 64 109 65 50 49 48 47 46 45 44 43 42 41 40 MPEG Clock input MPEG packet start input MPEG valid data input MPEG input transport stream MPEG data input 63 62 61 60 59 58 57 56 55 54 53 34 35 31 30 SCL SDA I2C bus 33 32 GND 18 17 16 15 14 CS DIR STR WAIT INT Host processor bus control 29 28 27 26 25 24 23 22 21 20 19 13 12 69 68 67 66 Host processor address bus 37 9 39 52 8 86 HA[25:15] VCC_ARRAY VCC_PROC VCC_TSI VCC_TSO VCC_DVB1 VCC_DVB2 MICLK MISTRT MIVAL MDI7 MDI6 MDI5 MDI4 MDI3 MDI2 MDI1 MDI0 MOCLK MOSTRT MOVAL MDO7 MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 MDO0 MPEG input stream from front end MPEG output stream to decoder RST CLK SCL SDA I2C bus SA1 SA0 I2C address A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 Host proc. address bus CS RD/DIR WR/STR WAIT/ACK INT Host proc. control signals EXTCS EXTINT Ext periph control DATOE# DATDIR ADOE# ADLE MPEG output stream to module A MICLKA MISTRTA MIVALA MDIA7 MDIA6 MDIA5 MDIA4 MDIA3 MDIA2 MDIA1 MDIA0 MPEG input stream from module A MOCLKA MOSTRTA MOVALA MDOA7 MDOA6 MDOA5 MDOA4 MDOA3 MDOA2 MDOA1 MDOA0 module A control signals control signals to both modules REG# OE# WE# IORD# IOWR# MPEG output stream to module B MICLKB MISTRTB MIVALB MDIB7 MDIB6 MDIB5 MDIB4 MDIB3 MDIB2 MDIB1 MDIB0 MPEG input stream from module B MOCLKB MOSTRTB MOVALB MDOB7 MDOB6 MDOB5 MDOB4 MDOB3 MDOB2 MDOB1 MDOB0 buffers control module B control signals GND_ARRAY GND_PROC GND_TSI GND_TSO GND_DVB1 GND_DVB2 RSTA CD1A# CD2A# CE1A# CE2A# RDY/IRQA# WAITA# modules power control RSTB CD1B# CD2B# CE1B# CE2B# RDY/IRQB# WAITB# VCCEN 110 92 105 116 114 112 107 103 99 96 94 118 127 125 84 80 78 76 74 5 3 1 120 72 7 82 87 101 122 123 88 97 89 90 108 91 104 115 113 111 106 102 98 95 93 117 126 124 83 79 77 75 73 4 2 128 119 71 6 81 85 100 121 70 CIMaX U2 36 38 51 64 109 65 50 49 48 47 46 45 44 43 42 41 40 63 62 61 60 59 58 57 56 55 54 53 MPEG clock output MPEG packet start output MPEG valid data output MPEG output transport stream MPEG data output VCC 34 35 31 30 33 32 GND 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 69 68 67 66 37 9 39 52 8 86 Title Chaining CIMaXes Size A2 Date: 9 Document Number {Doc} Friday, November 20, 1998 Rev 1.1 Sheet 1 of VCC_ARRAY VCC_PROC VCC_TSI VCC_TSO VCC_DVB1 VCC_DVB2 MICLK MISTRT MIVAL MDI7 MDI6 MDI5 MDI4 MDI3 MDI2 MDI1 MDI0 MOCLK MOSTRT MOVAL MDO7 MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 MDO0 MPEG input stream from front end MPEG output stream to decoder RST CLK SCL SDA I2C bus SA1 SA0 I2C address A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 Host proc. address bus CS RD/DIR WR/STR WAIT/ACK INT Host proc. control signals EXTCS EXTINT Ext periph control DATOE# DATDIR ADOE# ADLE GND_ARRAY GND_PROC GND_TSI GND_TSO GND_DVB1 GND_DVB2 MPEG output stream to module A MICLKA MISTRTA MIVALA MDIA7 MDIA6 MDIA5 MDIA4 MDIA3 MDIA2 MDIA1 MDIA0 MPEG input stream from module A MOCLKA MOSTRTA MOVALA MDOA7 MDOA6 MDOA5 MDOA4 MDOA3 MDOA2 MDOA1 MDOA0 module A control signals control signals to both modules RSTA CD1A# CD2A# CE1A# CE2A# RDY/IRQA# WAITA# REG# OE# WE# IORD# IOWR# MPEG output stream to module B MICLKB MISTRTB MIVALB MDIB7 MDIB6 MDIB5 MDIB4 MDIB3 MDIB2 MDIB1 MDIB0 MPEG input stream from module B MOCLKB MOSTRTB MOVALB MDOB7 MDOB6 MDOB5 MDOB4 MDOB3 MDOB2 MDOB1 MDOB0 buffers control module B control signals modules power control RSTB CD1B# CD2B# CE1B# CE2B# RDY/IRQB# WAITB# VCCEN 110 92 105 116 114 112 107 103 99 96 94 118 127 125 84 80 78 76 74 5 3 1 120 72 7 82 87 101 122 123 88 97 89 90 108 91 104 115 113 111 106 102 98 95 93 117 126 124 83 79 77 75 73 4 2 128 119 71 6 81 85 100 121 70 CIMaX 1 T90FJR Rev. A - 25-Oct-01 T90FJR Appendix A: Connecting CIMaXTM to an ST20 ST20 notMemCAS3 notMemRd notMemBE0 MemWait Interrupt0 CIMaXTM CS RD/DIR WR/STR WAIT/ACK INT This example shows how to connect a CIMaXTM to an ST20 microprocessor. This is just one possible configuration as there could be some other means of connecting the CIMaXTM to an ST20. In the above example, the full Bank3 is allocated to the CIMaXTM so the CIMaXTM is selected by notMemCAS3 signal. The CS input of the CIMaXTM should be configured to be active low as notMemCAS is active low so CSLVL bit in the host processor interface configuration register should be 0. The bus direction is controlled by notMemRd which is low during a read transfer. The RD/DIR input is used in direction control mode and the WR/STR input is used as strobe so RDIR should be 1. The RD/DIR input is low during a read transfer so RDIRLVL should be 0. The WR/STR input is low during a transfer so WSTRLVL bit should be 0. The bus wait cycles are inserted when MemWait is high at the beginning of a bus transfer. WAIT/ACK output is used in wait mode so WACK should be 0. MemWait input is active high so WLVL should be 1. As several peripherals can be and-wired to the MemWait pin of the ST20, the WAIT/ACK output must be an open-drain driver so the WDRV bit should be 0. The CIMaXTM interrupt output is wired to the Interrupt 0 input of the ST20. If CIMaXTM is the only source to the Interrupt0 input, the INT output driver can be configured to be a push-pull driver so INTDRV bit in the interrupt control register should be 1. Interrupt0 input of the ST20 is active-high so INTLVL bit should be 1. For details on how to configure the ST20 to match this configuration, please refer to the ST20 documentation. 10 Rev. A - 25-Oct-01 Appendix B: Connecting CIMaXTM to other processors The following provides an example on how to connect CIMaXTM with the VLSI VES2700 and LSI logic L64108 processors. Connection to Motorola MC68340 is the same as L64108. Signal CIMaXTM RD/DIR WR/STR CS WAIT/ACK INT ST20 notMemRd NotMemBE0 NotMemCAS3 MemWait Interrupt0 VES2700 B_Write GND DESCRAM_CS WAIT INT_EXT0 L64108/MC68340 R/W AS CS DSACK[0] INT0 The following table gives an example of the corresponding CIMaXTM configuration: Register 11 Microprocessor WAIT/ACK config Processor config Interrupt config ST20 03h (or 01h) 01h 06h (or 07h) VES2700 02h (or 00h) 03h 06h (or 07h) L64108/MC68340 06h (or 04h) 03h 02h (or 03h) T90FJR Rev. A - 25-Oct-01 T90FJR Appendix C: Out of Band connection When used in OpenCableTM compliant Host designs, the CIMaXTM requires additional glue logic to handle the Point-Of-Deployment (POD) module interface. Hardware differences between a standard DVB Common Interface implementation and an OpenCableTM implementation consist in the following: 1. Particular care must be taken for MOCLKA and MOCLKB connections to module slots. According to [6], MOCLKA/B are connected to pin 14 while they are connected to pin 57 in [2]. 2. An OpenCableTM receiver shall control the PCMCIA CE2# pin to enable the Extended Channel, as defined by SCTE DVS 131. 3. An OpenCableTM receiver shall include a DES-ECB descrambler and be able to simultaneously store one 64-bit key pair, as defined by the NRSS Part B Copy Protection Framework (EIA 679 Part B proposed revision -679BrAv5). 4. An OpenCableTM receiver shall include, as defined by SCTE DVS 131, both the OOB RF transmitter and receiver blocks, and manage the connection between these blocks and the POD module across the PCMCIA interface, if it wants to take advantage of the POD Out-of-band PHY and MAC capability. The CIMaXTM has built-in capability to address Point 2. It doesn't include any cryptographic function and as such a separate descrambler must be inserted between the TS output of the last CIMaXTM in the daisy chain and the demultiplexer to address Point 2. This application note doesn't intend to describe how the descrambler shall be connected to the CIMaXTM, however provisions shall be made to ensure that this descrambler could be driven by the CI DriverTM software stack. Concerning Point 3 and the OOB Channel, this application note describes how to route the six I/Os of the OOB RF transmitter and receiver blocks to two PCMCIA connectors. Additional glue logic is used to multiplex these six OOB signals with Host address signals A4 to A9, as required by SCTE DVS 131. This implementation adds two static control signals OOBEN (activation control of OOB mode) and OOBSEL (selection of which one of the 2 modules is connected to the OOB transceiver) that shall be directly driven by the Host Processor and the CI Driver software stack OOBEN 0 0 1 1 OOBSEL 0 1 0 1 Comment OOB I/Os are not routed OOB I/Os are not routed OOB I/Os are routed to slot A OOB I/Os are routed to slot B 12 Rev. A - 25-Oct-01 The following Bill Of Materials (BOM) applies: Description CIMaXTM (103563) PCMCIA Connector 74HCT373 74HCT245 74HCT257 74HCT02 Quantity 1x 2x 2x 1x 3x 1x Figure 5. Out of band connection U13 74HCT257 JP5 20 19 46 47 48 49 50 53 54 55 56 U14 36 38 51 64 109 65 50 49 48 47 46 45 44 43 42 41 40 63 62 61 60 59 58 57 56 55 54 53 34 35 31 30 33 32 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 69 68 67 66 37 9 39 52 8 86 VCC_ARRAY VCC_PROC VCC_TSI VCC_TSO VCC_DVB1 VCC_DVB2 MICLK MISTRT MIVAL MDI7 MDI6 MDI5 MDI4 MDI3 MDI2 MDI1 MDI0 MOCLK MOSTRT MOVAL MDO7 MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 MDO0 MPEG input stream from front end MPEG output stream to decoder RST CLK SCL SDA I2C bus SA1 SA0 I2C address A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 Host proc. address bus CS Host proc. RD/DIR control WR/STR WAIT/ACK signals INT EXTCS EXTINT Ext periph control DATOE# DATDIR ADOE# ADLE buffers control GND_ARRAY GND_PROC GND_TSI GND_TSO GND_DVB1 GND_DVB2 MPEG output stream to module A MPEG input stream from module A module A control signals control signals to both modules MPEG output stream to module B MPEG input stream from module B module B control signals modules power control MICLKA MISTRTA MIVALA MDIA7 MDIA6 MDIA5 MDIA4 MDIA3 MDIA2 MDIA1 MDIA0 MOCLKA MOSTRTA MOVALA MDOA7 MDOA6 MDOA5 MDOA4 MDOA3 MDOA2 MDOA1 MDOA0 RSTA CD1A# CD2A# CE1A# CE2A# RDY/IRQA# WAITA# REG# OE# WE# IORD# IOWR# MICLKB MISTRTB MIVALB MDIB7 MDIB6 MDIB5 MDIB4 MDIB3 MDIB2 MDIB1 MDIB0 MOCLKB MOSTRTB MOVALB MDOB7 MDOB6 MDOB5 MDOB4 MDOB3 MDOB2 MDOB1 MDOB0 RSTB CD1B# CD2B# CE1B# CE2B# RDY/IRQB# WAITB# VCCEN 110 92 105 116 114 112 107 103 99 96 94 R5 56. 14 62 63 64 65 66 37 38 39 40 41 118 127 125 84 80 78 76 74 5 3 1 61 7 42 9 15 44 45 60 16 120 72 7 82 87 101 122 MICLK MIVAL MISTRT MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 MOCLK MOVAL MOSTRT MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 REG CE1 CE2 OE WE/PGM IORD IOWR INPACK IREQ 68 35 GND 34 GND 1 GND GND 123 88 97 89 90 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 CTX/A4 ITX/A5 ETX/A6 QTX/A7 CRX/A8 DRX/A9 A10 A11 A12 A13 30 31 32 2 3 4 5 6 29 28 27 26 25 24 23 22 12 11 8 10 21 13 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 7 9 12 RESET 1A 1B 2A 2B 3A 3B 4A 4B 2Y 3Y 4Y 117 126 124 83 79 77 75 73 4 2 128 14 62 63 64 65 66 37 38 39 40 41 119 71 6 81 85 100 121 70 61 7 42 9 15 44 45 60 16 CIMaX MICLK MIVAL MISTRT MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 MOCLK MOVAL MOSTRT MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 REG CE1 CE2 OE WE/PGM IORD IOWR INPACK IREQ 6 U16 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 43 57 59 33 18 52 2 3 4 5 6 7 8 9 74HCT02 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 68 35 GND 34 GND 1 GND GND RESET 18 17 16 15 14 13 12 11 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 U15C 8 9 U15D 11 U17 2 5 6 9 12 15 16 19 OOBSEL 13 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 HA0 HA1 HA2 HA3 HA4 HA5 HA6 HA7 12 74HCT02 HD[7:0] HA[15:0] 1 OC 11 G Host processor address and data busses VCC 74AHCT373 30 31 32 2 3 4 5 6 29 28 27 26 25 24 23 22 12 11 8 10 21 13 43 57 59 33 18 52 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 R12 R13 R14 10k 10k 10k U18 2 5 6 9 12 15 16 19 MA8 MA9 MA10 MA11 MA12 MA13 MA0 MA1 MA2 MA3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 VCC R7 R8 R9 10k 10k 10k 1 OC 11 G U19 2 3 5 6 11 10 14 13 74AHCT373 MA10 MA11 MA12 MA13 MA4 MA8 MA9 7 9 1A 1B 2A 2B 3A 3B 4A 4B 1Y 2Y 3Y 4Y 4 ITX 7 ETX 9 QTX 12 Out Of Band outputs 15 1 G A/B U20 4 12 58 51 VCC 17 VCC 1Y 1A 1B 2A 2B 3A 3B 4A 4B 2Y 3Y 4Y 2 3 5 6 11 10 14 13 74HCT257 GND U21 18 16 14 12 9 7 5 3 15 G 1 A/B PCMCIA SOCKET GND Out Of Band control 74HCT02 74AHCT245 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 OOBEN 10 19 G 1 DIR 58 36 CD1 67 CD2 VS1 VS2 WAIT IOIS16 VPP1 VPP2 3 5 MA10 MA11 MA12 MA13 R6 10k A0 A1 A2 A3 CTX/A4 ITX/A5 ETX/A6 QTX/A7 CRX/A8 DRX/A9 A10 A11 A12 A13 2 1 4 51 VCC 17 VCC D0 D1 D2 D3 D4 D5 D6 D7 U15A DRX GND MA4 MA8 MA9 10k JP5 CRX U15B R5 20 19 46 47 48 49 50 53 54 55 56 CTX 74HCT02 PCMCIA SOCKET R6 56. Out Of Band inputs 2 3 5 6 11 10 14 13 15 G 1 A/B 36 CD1 67 CD2 VS1 VS2 WAIT IOIS16 VPP1 VPP2 1Y MA0 MA1 MA2 MA3 GND 108 91 104 115 113 111 106 102 98 95 93 4 74HCT257 GND R15 R16 R17 10k VCC 10k 10k 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 2 4 6 8 11 13 15 17 MA5 MA6 MA7 1 1G 19 2G GND 74HCT244 R10 10k Title out of band connection R11 10k Size A3 Date: 13 Document Number {Doc} Friday, December 17, 1999 Rev 1.0 Sheet 5 of 6 T90FJR Rev. A - 25-Oct-01 T90FJR Appendix D: External peripheral connection The following is an example of connecting a TL16C550 UART to the CIMaXTM. For more details about external device connection refer to chapter. Because EXTCS pin is in high impedance before VCCEN activation, it is recommended to add an external pull-up or pull-down according to its inactive level configured in Destination Select register (not drawn below). Figure 6. Connection of a UART to CiMaXTM U1 36 38 51 64 109 65 50 49 48 47 46 45 44 43 42 41 40 63 62 61 60 59 58 57 56 55 54 53 34 35 31 30 33 32 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 69 68 67 66 37 9 39 52 8 86 VCC_ARRA Y VCC_PRO C VCC_TS VCC_TS I VCC_DVB O 1 VCC_DVB 2 MICLK MISTRT MIVAL MDI7 MDI6 MDI5 MDI4 MDI3 MDI2 MDI1 MDI0 MOCLK MOSTRT MOVA L MDO7 MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 MDO0 MPEG input strea m from front end MPEG outpu tstrea m to decode r RST CLK SCL SDA SA1 SA0 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 I2C bus I2C address Host proc. addres sbus CS# RD/DIR WR/ST R WAIT/AC K INT Host proc. control signals EXTCS EXTINT Ext control periph DATOE DATDIR ADOE ADLE GND_ARRA Y GND_PRO C GND_TS I GND_TS GND_DVB O 1 GND_DVB 2 CIMaX MPEG outpu tstrea m to modul e A MICLK MISTRT A A MIVAL AMDIA7 MDIA6 MDIA5 MDIA4 MDIA3 MDIA2 MDIA1 MDIA0 MPEG input strea m from modul e A MOCLK MOSTRT A A MOVAL AMDOA7 MDOA6 MDOA5 MDOA4 MDOA3 MDOA2 MDOA1 MDOA0 module A control signals control signals to both module s MPEG outpu tstrea m to modul e B MPEG input strea m from modul e B buffer scontrol module B control signals module spowe rcontrol RSTA CD1A# CD2A# CE1A # CE2A RDY/IRQA # # WAITA # REG# OE# WE# IORD# IOWR # MICLK MISTRT B B MIVAL BMDIB7 MDIB6 MDIB5 MDIB4 MDIB3 MDIB2 MDIB1 MDIB0 MOCLK MOSTRT B B MOVAL BMDOB7 MDOB6 MDOB5 MDOB4 MDOB3 MDOB2 MDOB1 MDOB0 RSTB CD1B# CD2B# CE1B CE2B # RDY/IRQB # # WAITB # VCCEN 110 92 105 116 114 112 107 103 99 96 94 118 127 125 84 80 78 76 74 5 3 1 120 72 7 82 87 101 122 123 88 97 89 90 108 91 104 115 113 111 106 102 98 95 93 117 126 124 83 79 77 75 73 4 2 128 HD[7:0 ] U2 17 10 13 36 37 11 40 41 43 42 38 35 26 27 32 18 19 BAUDOU T RCLK SOUT RTS DTR SIN CTS DSR RI DCD OUT1 OUT2 DDIS TXRDY RXRDY XIN XOUT TL16C550 A D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 WR1 RD1 WR2 RD2 CS0 CS1 CS2 ADS INTRPT MR 2 3 4 5 6 7 8 9 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 31 30 29 HA0 HA1 HA2 20 24 HA[2:0 ] 21 25 VCC 14 15 16 28 33 39 GND 119 71 6 81 85 100 121 70 14 Rev. A - 25-Oct-01 Documents 1. PC Card Standard March 1997 2. Common Interface Specification for Conditional Access and other Digital Video Broadcasting Decoder Applications, February 1997, EN 5022. 3. Guidelines for implementation and use of the common interface for DVB decoder applications 4. Errata in EN 50221 and the Cenelec report [3] - CIT057 - rev6 5. I2C standard. Philips data handbook ref: IC12 6. Point-of-Deployment (POD) Module Interface proposal. SCTE DVS 131 Rev 10; October 4, 1999 CIMaXTM, CI PackTM and CI Pack+TM are registered trademark of SCM Microsystems. All other trademarks are the property of their respective companies. 15 T90FJR Rev. A - 25-Oct-01 Atmel Wireless & Microcontrollers Sales Offices France 3, Avenue du Centre 78054 St.-Quentin-en-Yvelines Cedex France Tel: 33130 60 70 00 Fax: 33130 60 71 11 Germany Erfurter Strasse 31 85386 Eching Germany Tel: 49893 19 70 0 Fax: 49893 19 46 21 Kruppstrasse 6 45128 Essen Germany Tel: 492 012 47 30 0 Fax: 492 012 47 30 47 Theresienstrasse 2 74072 Heilbronn Germany Tel: 4971 3167 36 36 Fax: 4971 3167 31 63 Italy Via Grosio, 10/8 20151 Milano Italy Tel: 390238037-1 Fax: 390238037-234 Spain Principe de Vergara, 112 28002 Madrid Spain Tel: 3491564 51 81 Fax: 3491562 75 14 Sweden Kavallerivaegen 24, Rissne 17402 Sundbyberg Sweden Tel: 468587 48 800 Fax: 468587 48 850 United Kingdom Easthampstead Road Bracknell, Berkshire RG12 1LX United Kingdom Tel: 441344707 300 Fax: 441344427 371 USA 2325 Orchard Parkway San Jose California 95131 USA-California Tel: 1408441 0311 Fax: 1408436 4200 1465 Route 31, 5th Floor Annandale New Jersey 08801 USA-New Jersey Tel: 1908848 5208 Fax: 1908848 5232 Hong Kong 77 Mody Rd., Tsimshatsui East, Rm.1219 East Kowloon Hong Kong Tel: 85223789 789 Fax: 85223755 733 Korea Ste.605,Singsong Bldg. Youngdeungpo-ku 150-010 Seoul Korea Tel: 8227851136 Fax: 8227851137 Singapore 25 Tampines Street 92 Singapore 528877 Rep. of Singapore Tel: 65260 8223 Fax: 65787 9819 Taiwan Wen Hwa 2 Road, Lin Kou Hsiang 244 Taipei Hsien 244 Taiwan, R.O.C. Tel: 88622609 5581 Fax: 88622600 2735 Japan 1-24-8 Shinkawa, Chuo-Ku 104-0033 Tokyo Japan Tel: 8133523 3551 Fax: 8133523 7581 Web site http://www.atmel-wm.com (c) Atmel Nantes SA, 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Printed on recycled paper.